The present invention concerns a computing system with an input/output bus and more particularly concerns multiple segmenting of main memory to streamline data paths in the computing system.
In computing systems which function as network servers, it is increasingly common to utilize multiple central processing units(CPUs) interconnected by a host (processor/memory) bus. In such a system a main memory for the system is also connected to the host bus. Communication with I/O devices is generally through an I/O bus, to the host bus through a bus bridge.
Operation of a bus bridge for input/output in a multiprocessor system utilizes a significant amount of the host bandwidth. In addition to the bandwidth required for data transfers over the host bus, the bus bridge needs to implement all the features of both the host bus and the I/O bus.
For example when a bus bridge accesses the main memory in a system where one or more processors utilizes a cache, it is necessary to take steps to insure the integrity of data accessed in memory. For example, when the bus bridge accesses (writes or reads) data from main memory, it is important to determine whether an updated version of the data resides in the cache of a processor on the system. If an updated version of the data exist, something must be done to insure that the bus bridge accesses the updated version of the data. An operation that assures that the updated version of the data is utilized in a memory reference is referred to herein as a cache coherence operation. Various schemes are used to insure coherence of data accessed by bus bridge from the system memory. For example, in some systems caches are flushed prior to performing I/O operations.
Likewise, some I/O buses require that data transactions be atomic. That is, other transactions need to be "locked out" during atomic data transactions. A bus bridge which interfaces with such an I/O bus needs to be able to implement this feature. However, when a bus bridge performs atomic transactions, this slows down overall system performance.
When there are multiple processors in a system competing with the bus bridge for access to memory over the host bus, this can slow the access of the bus bridge to main memory and thus cause a significant bottleneck in performance in system I/O.